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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10153362 B1

PDFFull Text
Date of Patent:
Dec. 11, 2018

Filed:

Oct. 27, 2016

Semiconductor device

Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Gilberto Curatola, Villach, AT;

Oliver Haeberlen, St. Magdalen, AT;

Assignee:

Infineon Technologies Austria AG, Villach, AT;

Attorney:

Murphy, Bilak & Homiller, PLLC

Primary Examiner:

Julio J Maldonado

Assistant Examiner:

Stanetta Isaac

Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 29/0891 (2013.01); H01L 29/1058 (2013.01); H01L 29/1066 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/402 (2013.01); H01L 29/42316 (2013.01); H01L 29/7786 (2013.01); H01L 29/4236 (2013.01);
Abstract

In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.

Find Patent Forward Citations

Curatola, Gilberto. (2018). Semiconductor device (U.S. Patent No. 10153362). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10153362

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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