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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10153356 B1

PDFFull Text
Date of Patent:
Dec. 11, 2018

Filed:

Mar. 15, 2017

Method of manufacturing semiconductor device, and semiconductor device

Applicant:

Toyoda Gosei Co., Ltd., Kiyosu-shi, JP;

Inventors:

Tohru Oka, Kiyosu, JP;

Nariaki Tanaka, Kiyosu, JP;

Assignee:

TOYODA GOSEI CO., LTD., Kiyosu-Shi, Aichi-Ken, JP;

Attorney:

McGinn IP Law Group, PLLC

Primary Examiner:

Dung Le

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/207 (2006.01); H01L 29/78 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66734 (2013.01); H01L 21/2258 (2013.01); H01L 21/266 (2013.01); H01L 21/26546 (2013.01); H01L 21/26553 (2013.01); H01L 21/3245 (2013.01); H01L 29/1095 (2013.01); H01L 29/2003 (2013.01); H01L 29/207 (2013.01); H01L 29/66522 (2013.01); H01L 29/7809 (2013.01); H01L 29/7813 (2013.01);
Abstract

A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type impurity is provided. A method of manufacturing a semiconductor device having a trench gate structure comprises an n-type semiconductor region forming process. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which a p-type impurity contained in a p-type semiconductor layer is diffused is formed in at least part of an n-type semiconductor layer that is located below an n-type semiconductor region.

Find Patent Forward Citations

Oka, Tohru. (2018). Method of manufacturing semiconductor device, and semiconductor device (U.S. Patent No. 10153356). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10153356

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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