The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Nov. 27, 2017
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Zheng Tao, Heverlee, BE;

Boon Teik Chan, Leuven, BE;

Soon Aik Chew, Heverlee, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/3065 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); B82Y 10/00 (2011.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); B82Y 10/00 (2013.01); H01L 21/0217 (2013.01); H01L 21/02126 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/66 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 21/02271 (2013.01); H01L 21/02282 (2013.01);
Abstract

A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.


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