The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Jul. 26, 2017
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, Guangdong, CN;

Inventor:

Jinming Li, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/385 (2006.01); H01L 21/477 (2006.01); H01L 29/24 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01); H01L 21/443 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/127 (2013.01); H01L 21/02488 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 21/385 (2013.01); H01L 21/443 (2013.01); H01L 21/477 (2013.01); H01L 27/1225 (2013.01); H01L 29/24 (2013.01); H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01); H01L 27/3262 (2013.01);
Abstract

The present disclosure provides a method for manufacturing a thin film transistor comprising: forming a buffer layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode sequentially on a substrate, wherein on both sides of the first region of the oxide semiconductor layer are second regions where the gate electrode is exposed; forming an aluminum layer covering the buffer layer, the second regions of the oxide semiconductor layer and the gate electrode by a physical vapor deposition method, and annealing the aluminum layer, making the second regions of the oxide semiconductor layer being doped by aluminum ions to form conductor regions; etching the remaining aluminum layer after the annealing treatment; renovating the etched surfaces of the buffer layer, the gate electrode and the conductor regions, and oxidizing the conductor regions; stacking an insulating layer, and forming a source electrode and a drain electrode on the insulating layer.


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