The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2018
Filed:
Jul. 25, 2017
Renesas Electronics Corporation, Tokyo, JP;
Tamotsu Ogata, Tokyo, JP;
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Abstract
A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PWin a memory cell regionA in a semiconductor substrateand an MISFET arranged in a p-type well PW(active region) or an n-type well (active region) in a peripheral circuit regionA is constructed as follows. The surface of an element isolation region STIsurrounding the p-type well PWis set lower than the surface of an element isolation region STIsurrounding the p-type well PWor the n-type well (H<H). By making the surface of the element isolation region STIreceded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STIis not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.