The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Dec. 21, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si,Gyeonggi-do, KR;

Inventors:

Se Jung Park, Hwaseong-si, KR;

Ju-Hyun Kim, Hwaseong-si, KR;

Hoyoung Kim, Seongnam-si, KR;

Boun Yoon, Seoul, KR;

TaeYong Kwon, Suwon-si, KR;

Sangkyun Kim, Hwaseong-si, KR;

Sanghyun Park, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 21/84 (2006.01); H01L 21/3105 (2006.01); H01L 21/306 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/30625 (2013.01); H01L 21/31053 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01);
Abstract

A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.


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