The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2018
Filed:
Mar. 26, 2015
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Aravindan J. Busi, Bangalore, IN;
Kevin W. Gorman, Fairfax, VT (US);
Deepak I. Hanagandi, Jamkhandi, IN;
Kiran K. Narayan, Motinagar, IN;
Michael R. Ouellette, Westford, VT (US);
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/56 (2006.01); G11C 29/44 (2006.01); G11C 29/26 (2006.01); G11C 29/12 (2006.01); G11C 29/04 (2006.01); G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
G11C 29/56008 (2013.01); G01R 31/3187 (2013.01); G11C 29/12 (2013.01); G11C 29/44 (2013.01); G11C 29/4401 (2013.01); G11C 2029/0401 (2013.01); G11C 2029/2602 (2013.01); G11C 2029/5602 (2013.01); G11C 2029/5606 (2013.01);
Abstract
A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.