The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Nov. 21, 2017
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

James B. Williams, San Jose, CA (US);

Shawn Adam Clayton, San Jose, CA (US);

Maria Clara Gutierrez, San Jose, CA (US);

Alexander Nicolson, IV, San Jose, CA (US);

James Winston Smart, San Jose, CA (US);

John Leland Wood, San Jose, CA (US);

David James Duckman, San Jose, CA (US);

Carl John Lindeborg, San Jose, CA (US);

William Irving Leavitt, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/16 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/16 (2013.01); G06F 13/385 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.


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