The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Feb. 09, 2012
Applicants:

Michael Fetterman, Boxborough, MA (US);

Stewart Glenn Carlton, Madison, AL (US);

Jack Hilaire Choquette, Palo Alto, CA (US);

Shirish Gadre, Fremont, CA (US);

Olivier Giroux, San Jose, CA (US);

Douglas J. Hahn, Los Altos, CA (US);

Steven James Heinrich, Madison, AL (US);

Eric Lyell Hill, Palo Alto, CA (US);

Charles Mccarver, Madison, AL (US);

Omkar Paranjape, Austin, TX (US);

Anjana Rajendran, San Jose, CA (US);

Rajeshwaran Selvanesan, Milpitas, CA (US);

Inventors:

Michael Fetterman, Boxborough, MA (US);

Stewart Glenn Carlton, Madison, AL (US);

Jack Hilaire Choquette, Palo Alto, CA (US);

Shirish Gadre, Fremont, CA (US);

Olivier Giroux, San Jose, CA (US);

Douglas J. Hahn, Los Altos, CA (US);

Steven James Heinrich, Madison, AL (US);

Eric Lyell Hill, Palo Alto, CA (US);

Charles McCarver, Madison, AL (US);

Omkar Paranjape, Austin, TX (US);

Anjana Rajendran, San Jose, CA (US);

Rajeshwaran Selvanesan, Milpitas, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3861 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3887 (2013.01);
Abstract

One embodiment of the present disclosure sets forth an optimized way to execute pre-scheduled replay operations for divergent operations in a parallel processing subsystem. Specifically, a streaming multiprocessor (SM) includes a multi-stage pipeline configured to insert pre-scheduled replay operations into a multi-stage pipeline. A pre-scheduled replay unit detects whether the operation associated with the current instruction is accessing a common resource. If the threads are accessing data which are distributed across multiple cache lines, then the pre-scheduled replay unit inserts pre-scheduled replay operations behind the current instruction. The multi-stage pipeline executes the instruction and the associated pre-scheduled replay operations sequentially. If additional threads remain unserviced after execution of the instruction and the pre-scheduled replay operations, then additional replay operations are inserted via the replay loop, until all threads are serviced. One advantage of the disclosed technique is that divergent operations requiring one or more replay operations execute with reduced latency.


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