The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2018
Filed:
Nov. 30, 2017
Applicant:
Ip Gem Group, Llc, Irvine, CA (US);
Inventors:
Rino Micheloni, Turate, IT;
Antonio Aldarese, Vimercate, IT;
Salvatrice Scommegna, Cornate d'Adda, IT;
Assignee:
IP GEM GROUP, LLC, Irvine, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G06F 3/06 (2006.01); G06F 12/00 (2006.01); G11C 16/16 (2006.01); G11C 16/32 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0652 (2013.01); G06F 3/0604 (2013.01); G06F 3/0688 (2013.01); G06F 12/00 (2013.01); G11C 16/16 (2013.01); G11C 16/32 (2013.01); G11C 16/0483 (2013.01); G11C 16/349 (2013.01); G11C 2216/20 (2013.01);
Abstract
A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for incrementing the number of program and erase cycles when the erase-suspend limit has been reached.