The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Oct. 09, 2017
Applicant:

Linear Technology Corporation, Milpitas, CA (US);

Inventors:

Brett Warneke, Castro Valley, CA (US);

Maxim Moiseev, Santa Clara, CA (US);

Assignee:

Linear Technology Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/12 (2006.01); G06F 9/44 (2018.01); H03L 5/02 (2006.01); H03L 7/18 (2006.01); H04W 52/02 (2009.01); H04B 1/00 (2006.01); G06F 9/445 (2018.01); G06F 1/14 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3243 (2013.01); G06F 1/12 (2013.01); G06F 1/3234 (2013.01); G06F 1/3287 (2013.01); G06F 1/3293 (2013.01); G06F 9/44505 (2013.01); H03L 5/02 (2013.01); H03L 7/18 (2013.01); H04B 1/0003 (2013.01); H04W 52/0203 (2013.01); H04W 52/0209 (2013.01); G06F 1/14 (2013.01); G06F 1/3237 (2013.01); Y02D 10/171 (2018.01); Y02D 70/00 (2018.01); Y02D 70/122 (2018.01); Y02D 70/144 (2018.01); Y02D 70/22 (2018.01);
Abstract

A network device includes a network interface circuit, a microprocessor, a timing circuit, and a microsequencer. The timing circuit is configured to, based on a primary timing signal, generate a time signature and switch the network device from an inactive state to an active state when the time signature satisfies a predetermined threshold length of time for packet transmission. The microsequencer circuit is configured to, in response to the network device being switched to the active state, activate and configure the network interface circuit for the packet transmission, independent of the microprocessor and delays encountered by the microprocessor. The device also reduces energy consumption by using a lower frequency secondary oscillator to maintain timing information when a higher frequency primary oscillator is inactivated.


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