The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Jul. 08, 2013
Applicant:

Morpho, Issy-les-Moulineaux, FR;

Inventors:

Thanh Ha Le, Issy-les-Moulineaux, FR;

Julien Bringer, Issy-les-Moulineaux, FR;

Louis-Philippe Goncalves, Issy-les-Moulineaux, FR;

Maël Berthier, Issy-les-Moulineaux, FR;

Assignee:

IDEMIA IDENTITY & SECURITY FRANCE, Issy les Moulineaux, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 21/54 (2013.01); G06F 21/77 (2013.01);
U.S. Cl.
CPC ...
H04L 63/14 (2013.01); G06F 21/54 (2013.01); G06F 21/77 (2013.01);
Abstract

A functional program stored in a memory area of an electronic card may be protected against an attack by disturbance of electrical origin intended to modify at least one logic state of at least one code of this program. The method may include: a storage step during which codes of the functional program and codes of a check program intended to check the logical behavior of the functional program are stored in the memory of the card; and a step of executing at least one code of the functional program followed by a step of checking the logic states of the functional program by executing the check program. During the storage step, the codes of the check program are stored in a memory area formed by addresses that are defined so that the attack by disturbance of electrical origin has no influence on the logic states of this program.


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