The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Dec. 23, 2017
Applicant:

Avnera Corporation, Beaverton, OR (US);

Inventors:

Wai Lee, Portland, OR (US);

Jianping Wen, Tigard, OR (US);

Garry N. Link, Pacific City, OR (US);

Assignee:

Avnera Corporation, Beaverton, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/38 (2006.01); H03M 1/46 (2006.01); H03M 1/44 (2006.01); H03M 1/10 (2006.01); H03M 1/18 (2006.01);
U.S. Cl.
CPC ...
H03M 1/462 (2013.01); H03M 1/1033 (2013.01); H03M 1/447 (2013.01); H03M 1/188 (2013.01); H03M 1/468 (2013.01);
Abstract

The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.


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