The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Aug. 28, 2016
Applicant:

Deyi Pi, Laguna Niguel, CA (US);

Inventor:

Deyi Pi, Laguna Niguel, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/197 (2006.01); H03M 1/66 (2006.01); H03L 7/10 (2006.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1974 (2013.01); H03L 7/0802 (2013.01); H03L 7/104 (2013.01); H03M 1/662 (2013.01);
Abstract

Various embodiments of fractional-N phase-locked loop (PLL) frequency synthesizers based on digital-to-analog conversion (DAC) are disclosed. In some embodiments, a PLL frequency synthesizer includes a phase-frequency detector, a voltage controlled oscillator (VCO) coupled to the phase-frequency detector, and a digital-to-analog converter (DAC) coupled between an input of the phase-frequency detector and an output of the VCO within a feedback path of the PLL frequency synthesizer. The phase-frequency detector is configured to receive a reference input clock and an output signal of the DAC as a feedback input clock. Furthermore, the DAC receives an output clock from the VCO and a digital control signal comprising frequency and phase information for synthesizing the feedback input clock. The disclosed DAC-based PLL frequency synthesizers do not require any frequency divider in a feedback path of the PLL, thereby significantly reducing power consumption and noise levels.


Find Patent Forward Citations

Loading…