The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2018
Filed:
Nov. 10, 2016
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Ajay Kumar Kosaraju, Singapore, SG;
Guolei Yu, Singapore, SG;
Yi-Cheng Wan, Singapore, SG;
Sugato Mukherjee, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/157 (2006.01); G01R 19/165 (2006.01); H02M 1/08 (2006.01); H02M 3/156 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/157 (2013.01); G01R 19/16571 (2013.01); H02M 1/08 (2013.01); H02M 3/1563 (2013.01); H02M 2001/0009 (2013.01); H02M 2001/0032 (2013.01);
Abstract
A duty cycle estimation circuit includes a latch circuit that receives a clock signal for a voltage regulator. The latch circuit outputs a duty cycle estimate. The duty cycle estimation circuit also includes a low pass filter coupled to an output of the latch circuit to receive the duty cycle estimate. The duty cycle estimation circuit further includes a comparator that receives, as input, an output of the low pass filter and a voltage regulator output. The comparator feeds back a feedback signal to the latch circuit.