Fault current-suppressing damper topology circuit and control method thereof and converter

Abstract

Disclosed are a fault current-suppressing damper topology circuit and a control method thereof and a converter. An anode of a separate diode is connected to a positive electrode of a second switch module, a cathode of the separate diode is connected to one end of an energy storage capacitor, and the other end of the energy storage capacitor is connected to a negative electrode of a first switch module; a damping resistor is connected in parallel with an arrester and then with the first switch module; a bypass switch is connected in parallel between a terminal xand a terminal xof the damper topology circuit; a power supply system acquires energy from the energy storage capacitor and supplies power to a control system; and the control system controls an operating state of the damper topology circuit by controlling the bypass switch, the first switch module and the second switch module. The fault current-suppressing damper topology circuit is applied to voltage source converters. In case of a DC fault, stress resulting from fault currents is reduced by use of a damping resistor, thereby avoiding damages to a device and achieving self-power supply, modularization and independent control. The fault current-suppressing damper topology circuit can be flexibly applied to various types of voltage source converters and has outstanding economic efficiency and technicality.