The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Jan. 26, 2017
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Jaume Roig-Guitart, Oudenaarde, BE;

Filip Bauwens, Loppem, BE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/808 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 29/8083 (2013.01);
Abstract

In at least some embodiments, a semiconductor device structure comprises a first surface comprising a source and a gate; a second surface comprising a drain; a substrate of a first type, wherein the substrate is in contact with the drain; a first column in contact with the substrate and the first surface of the device, the first column comprising a dielectric material; and a mirroring axis, wherein a centerline of the first column is disposed along the mirroring axis, forming a first device side and a second device side, wherein the first device side mirrors the second device side. The first device side comprises a column of a second type in contact with the first column, the substrate, and the first surface of the device; a second column of the first type in contact with the substrate and the second column; a third column of the first type in contact with the substrate and the second column; a first region of the first type disposed in contact with the third column; a second region of the first type disposed in contact with the source and with a third region of the first type; and a first trench comprising the second type and a first region of the second type, wherein the first region of the second type is in contact with a gate region.


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