The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2018
Filed:
Oct. 31, 2017
Psemi Corporation, San Diego, CA (US);
Buddhika Abesingha, Escondido, CA (US);
Simon Edward Willard, Irvine, CA (US);
Alain Duvallet, San Diego, CA (US);
Merlin Green, San Diego, CA (US);
Sivakumar Kumarasamy, San Diego, CA (US);
pSemi Corporation, San Diego, CA (US);
Abstract
Methods and structures for mitigating back gate effects in high voltage and low voltage semiconductor devices of a same integrated circuit fabricated in a silicon-on-insulator technology are described. According to one aspect, one or more resistive couplings are used to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage semiconductor devices. According to another aspect, an N-type implant that is biased through a resistive coupling is used to provide a high potential differential with respect to a substrate potential.