The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Sep. 19, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Jae Yong Cha, Seoul, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/1157 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); H01L 27/1157 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers.


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