The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Oct. 23, 2017
Applicant:

Dpix, Llc, Colorado Springs, CO (US);

Inventors:

Byung-Kyu Park, Colorado Springs, CO (US);

Karthik Nagarajan, Colorado Springs, CO (US);

Jungwon Park, Colorado Springs, CO (US);

Yang-Wen Chen, Fremont, CA (US);

Ick-Hwan Ko, Colorado Springs, CO (US);

Assignee:

DPIX, LLC, Colorado Springs, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/786 (2006.01); G02F 1/1362 (2006.01); H01L 27/146 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0266 (2013.01); G02F 1/136204 (2013.01); H01L 27/0288 (2013.01); H01L 27/0292 (2013.01); H01L 27/0296 (2013.01); H01L 27/14658 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H01L 28/40 (2013.01);
Abstract

An ESD circuit includes a first metal oxide channel device having a drain coupled to a first node, a source coupled to a second node, and a gate coupled to the first node; a second metal oxide channel device having a source coupled to the first node, a drain coupled to the second node, and a gate coupled to the second node; a first capacitor coupled between the first and second nodes proximate to the first metal oxide channel device; and a second capacitor coupled between the first and second nodes proximate to the second metal oxide channel device. The ESD circuit can further include a third capacitor coupled between the first and second nodes proximate to the first capacitor. The ESD circuit can further include a fourth capacitor coupled between the first and second nodes proximate to the second capacitor.


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