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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10147652 B1

PDFFull Text
Date of Patent:
Dec. 04, 2018

Filed:

Feb. 24, 2015

Method, apparatus and system for advanced channel cmos integration

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventor:

Srinivasa Banna, San Jose, CA (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:

Williams Morgan, P.C.

Primary Examiner:

Steven H Loke

Assistant Examiner:

Scott Stowe

Int. Cl.
CPC ...
H01L 29/38 (2006.01); H01L 21/8258 (2006.01); H01L 21/8252 (2006.01); H01L 29/20 (2006.01); H01L 29/161 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8258 (2013.01); H01L 21/8252 (2013.01); H01L 27/092 (2013.01); H01L 29/1054 (2013.01); H01L 29/161 (2013.01); H01L 29/20 (2013.01); H01L 29/66522 (2013.01); H01L 29/66568 (2013.01); H01L 29/7849 (2013.01); H01L 29/78603 (2013.01); H01L 29/78681 (2013.01); H01L 21/823807 (2013.01);
Abstract

At least one method, apparatus and system disclosed involves a semiconductor substrate on which NMOS and PMOS devices with enhanced current drives may be formed. A first substrate having an enhanced electron mobility is formed. A second substrate having an enhanced hole mobility is formed. The first substrate and the second substrate are bonded for forming a third substrate. A first channel on the third substrate characterized by the enhanced electron mobility is formed. A second channel on the third substrate characterized by the enhanced hole mobility is formed.

Find Patent Forward Citations

Banna, Srinivasa. (2018). Method, apparatus and system for advanced channel cmos integration (U.S. Patent No. 10147652). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10147652

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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