The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

May. 20, 2016
Applicant:

Panasonic Liquid Crystal Display Co., Ltd., Hyogo, JP;

Inventors:

Yoshihisa Ooishi, Hyogo, JP;

Genshiro Kawachi, Hyogo, JP;

Kazuo Kita, Hyogo, JP;

Toshikazu Koudo, Hyogo, JP;

Hideyuki Nakanishi, Hyogo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3648 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0218 (2013.01); G09G 2310/0281 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/067 (2013.01); G09G 2310/08 (2013.01);
Abstract

A display apparatus includes an image display region having pixels sectioned by scanning signal lines and video signal lines, scanning connecting lines, thin film transistors, selection signal lines connected to gate electrodes of the thin film transistors, plural ones of the thin film transistors connected to different ones of the scanning connecting lines being connected to one of the selection signal lines; and a scanning signal drive circuit. The scanning signal drive circuit performs a normal scanning mode in which pulse signals are supplied in turn to plural ones of the scanning connecting lines connected to the one of the selection signal lines, and in the normal scanning mode, a fall timing of the gate-on voltage differs from a fall timing of a last one of the pulse signals supplied to the plural ones of the scanning connecting lines during the selection period.


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