The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Nov. 08, 2016
Applicant:

The Regents of the University of California, Oakland, CA (US);

Inventors:

Kang L. Wang, Santa Monica, CA (US);

Hao-Yuan Chang, Folsom, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06N 7/08 (2006.01); G06N 7/00 (2006.01);
U.S. Cl.
CPC ...
G06N 7/08 (2013.01); G06N 7/005 (2013.01);
Abstract

A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.


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Wang, Kang. (2018). Self-organized critical cmos circuits and methods for computation and information processing (U.S. Patent No. 10147045). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10147045

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