The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Dec. 21, 2017
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventor:

Anthony J. Bybell, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/1027 (2016.01); G06F 1/32 (2006.01); G06F 12/0864 (2016.01); G11C 15/00 (2006.01); H04L 12/741 (2013.01); H04L 12/743 (2013.01); G06F 12/0842 (2016.01); G11C 5/14 (2006.01); G06F 17/30 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 1/3287 (2013.01); G06F 12/0842 (2013.01); G06F 12/0864 (2013.01); G11C 5/14 (2013.01); G11C 15/00 (2013.01); H04L 45/745 (2013.01); H04L 45/7457 (2013.01); G06F 17/30982 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/6032 (2013.04); G06F 2212/657 (2013.01); G06F 2212/683 (2013.01); G11C 2207/2263 (2013.01);
Abstract

A method and apparatus for reducing dynamic power consumption in a multi-thread content-addressable memory (CAM) is described. The disclosed apparatus includes a first input configured to receive a first virtual address corresponding to a first thread, a second input configured to receive a second virtual address corresponding to a second thread, a register bank including a plurality of registers each configured to store a binary word mapped to one of a plurality of physical addresses, a first comparator bank including a first plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration and configured to determine whether a first match is present, and a second comparator bank including a second plurality of comparators each coupled to one of the plurality of registers in a fully-associative configuration and configured to determine whether a second match is present.


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