The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Oct. 30, 2014
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Jonathan Hauke, Lexington, MA (US);

Benjamin Tsien, Fremont, CA (US);

Denis Rystsov, San Francisco, CA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01); G06F 21/75 (2013.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/324 (2013.01); G06F 1/329 (2013.01); G06F 21/755 (2017.08); Y02D 10/126 (2018.01); Y02D 10/24 (2018.01);
Abstract

The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes detecting a request to change a current performance state of a processor to a target performance state, and adjusting an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic operative to change the performance state of the at least one processing core based on the request. The system further includes performance state security logic operative to adjust, in response to the request, an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state.


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