The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Jun. 22, 2017
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

David Lewis, Toronto, CA;

Herman Henry Schmit, Palo Alto, CA (US);

Carl Ebeling, Redwood City, CA (US);

Assignee:

Altera Corporation, San Jose, unknown;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H03K 19/173 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/017581 (2013.01); H03K 19/017509 (2013.01); H03K 19/018521 (2013.01); H03K 19/1737 (2013.01);
Abstract

An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.


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