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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10141888 B1

PDFFull Text
Date of Patent:
Nov. 27, 2018

Filed:

Aug. 14, 2017

Double balanced mixer

Applicant:

Psemi Corporation, San Diego, CA (US);

Inventor:

Daoud Salameh, Reading, GB;

Assignee:

pSemi Corporation, San Diego, CA (US);

Attorneys:

Jaquez and Greenhaus LLP

Martin J. Jaquez, Esq.

John Land, Esq.

Primary Examiner:

Jung Kim

Int. Cl.
CPC ...
H03D 7/14 (2006.01); H01L 23/66 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 21/84 (2006.01); H01L 21/86 (2006.01); H01L 21/8238 (2006.01); H03D 7/02 (2006.01);
U.S. Cl.
CPC ...
H03D 7/1458 (2013.01); H01L 21/8238 (2013.01); H01L 21/84 (2013.01); H01L 21/86 (2013.01); H01L 23/66 (2013.01); H01L 27/0629 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 29/786 (2013.01); H01L 29/7838 (2013.01); H03D 7/02 (2013.01); H03D 7/1408 (2013.01); H03D 7/1441 (2013.01);
Abstract

A FET based double balanced mixer (DBM) that exhibits good conversion gain and IIP3 values and provides improved linearity and wide bandwidth. In one embodiment, a first balun is configured to receive a local oscillator (LO) signal and generate two balanced LO signals that are coupled to two corresponding opposing nodes of a four-node FET ring. A second balun is configured to pass an RF signal on the unbalanced side. The FET ring includes at least four FETs connected as branches of a ring, with the source of each FET connected to the drain of a next FET in the ring. Each FET is preferably fabricated as, or configured as, a low threshold voltage device having its gate connected to its drain, which causes the FET to operate as a diode, but with the unique characteristic of having close to a zero turn-on voltage.

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