The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2018
Filed:
Jun. 29, 2016
Philips Lighting Holding B.v., Eindhoven, NL;
Xianhui Zhang, Shanghai, CN;
Ken K. Li, Shanghai, CN;
Zhi Quan Chen, Shanghai, CN;
Junhu Liu, Shanghai, CN;
Ace Li, Shanghai, CN;
PHILIPS LIGHTING HOLDING B.V., Eindhoven, NL;
Abstract
The invention provides a power converter comprising: an input for receiving input power with a variable nominal mains level, wherein said variable nominal mains level falls within at least 90V to 240V; a main power switch (Q) driven by the input power, and a control circuit (Q, Q) for controlling a control current of the main power switch (Q), wherein the control circuit in (Q, Q) is adapted to sense the level of the input power and draw current from a control terminal of the power switch (Q) according to the level, and said control circuit is adapted to operate in linear region and increase the drawn current along with the increase of the level throughout the variable nominal mains level of the input power, wherein the control circuit comprises: a Darlington bridge with a first transistor (Q) and a second transistor (Q), the first transistor (Q) with a base terminal connected to a circuit position indicative of the voltage amplitude of the input power, the second transistor (Q) with a base terminal connected to an emitter terminal of the first transistor (Q) and a collector terminal connected to the control terminal of the main power switch (Q) and a collector terminal of the first transistor (Q); and a resistor network (R, R) coupled to the emitter of the second transistor (Q) for regulating the amplification of the second transistor (Q) and keep the second transistor (Q) working at linear region throughout the variable nominal mains level of the input power.