The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Jul. 21, 2016
Applicant:

Omnivision Technologies, Inc., Santa Clara, CA (US);

Inventors:

Bowei Zhang, Fremont, CA (US);

Duli Mao, Sunnyvale, CA (US);

Assignee:

OmniVision Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/02 (2006.01); H01L 27/14 (2006.01); H01L 31/10 (2006.01); G04F 10/00 (2006.01); H04N 5/374 (2011.01); H01L 31/0224 (2006.01); H01L 31/107 (2006.01); H01L 31/0216 (2014.01); H01L 27/146 (2006.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H01L 31/022416 (2013.01); G04F 10/005 (2013.01); H01L 27/1462 (2013.01); H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14634 (2013.01); H01L 27/14643 (2013.01); H01L 31/02027 (2013.01); H01L 31/02161 (2013.01); H01L 31/107 (2013.01); H04N 5/374 (2013.01); H04N 5/378 (2013.01);
Abstract

A photon detection device includes a single photon avalanche diode (SPAD) including a multiplication junction defined at an interface between n doped and p doped layers of the SPAD in a first region of a semiconductor layer. A vertical gate structure surrounds the SPAD in the semiconductor layer to isolate the SPAD in the first region from a second region of the semiconductor layer on an opposite side of the vertical gate structure. The SPAD laterally extends within the first region of semiconductor layer to the vertical gate structure. An inversion layer is generated in the SPAD around a perimeter of the SPAD proximate to the vertical gate structure in response to a gate bias voltage coupled to the vertical gate structure. The inversion layer isolates the SPAD from the second region of the semiconductor layer on the opposite side of the vertical gate structure.


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