The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Nov. 23, 2016
Applicant:

Imec Vzw, Leuven, BE;

Inventor:

Mikael Detalle, Limal, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 28/91 (2013.01); H01L 23/5223 (2013.01); H01L 28/92 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/14 (2013.01);
Abstract

The disclosed technology relates to a metal-insulator-metal capacitor (MIMCAP) integrated as part of a back-end-of-line of an integrated circuit (IC). In one aspect, a MIMCAP comprises a first planar electrode having perforations formed therethrough, and a metal-insulator-metal (MIM) stack lining inner surfaces of cavities formed in the perforations and extending into the substrate. The MIMCAP additionally comprises a second electrode having a planar portion and metal extensions extending from the planar portion into the cavities. The first electrode and the planar portion of the second electrode are formed of or comprise planar metal areas of the respective metallization levels, which can be formed by a damascene process, which allows for a reduction of the series resistance. A low aspect ratio can be obtained using one electrode having a 3D-structure (the electrode having extensions extending into the cavities).


Find Patent Forward Citations

Detalle, Mikael. (2018). Integrated circuit comprising a metal-insulator-metal capacitor and fabrication method thereof (U.S. Patent No. 10141394). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10141394

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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