Semiconductor memory device

Abstract

A semiconductor memory device includes a peripheral circuit element provided over a lower substrate; an upper substrate provided over an interlayer dielectric layer which partially covers the peripheral circuit element; a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate and a plurality of gate lines which are stacked over the upper substrate to surround the channel structure; and a plurality of transistors electrically coupling the gate lines to the peripheral circuit element. The transistors include a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction; a plurality of vertical channels passing through the gate electrode in the first direction and electrically coupled to the gate lines, respectively; and gate dielectric layers disposed between the vertical channels and the gate electrode.