The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Mar. 16, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Mukund Narasimhan, Bangalore, IN;

Sharad Kumar Gupta, Bangalore, IN;

Dharaneedharan Shanmugasundaram, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 7/02 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1689 (2013.01); G11C 7/02 (2013.01); G11C 7/1087 (2013.01); G11C 7/12 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 2207/2209 (2013.01); G11C 2207/2245 (2013.01);
Abstract

In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.


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Narasimhan, Mukund. (2018). Noise immune data path scheme for multi-bank memory architecture (U.S. Patent No. 10140224). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10140224

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