The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Sep. 06, 2016
Applicant:

Accelstor, Inc., Taipei, TW;

Inventors:

Shih-Chiang Tsao, Taipei, TW;

Ting-Fang Chien, Taipei, TW;

An-Nan Chang, Taipei, TW;

Assignee:

ACCELSTOR, INC., Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0641 (2013.01); G06F 3/0608 (2013.01); G06F 3/0659 (2013.01); G06F 3/0665 (2013.01); G06F 3/0674 (2013.01); G06F 12/0253 (2013.01); G06F 12/0292 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/152 (2013.01);
Abstract

The data storage system includes a memory, a hard disk, and a processing unit. A first logical address and a second logical address in a first logical block of the memory correspond to a piece of duplicated data, and the duplicated data is stored in two physical pages in the hard disk. When executing a de-duplication command, the processing unit transfers the duplicated data to a physical page mapped to a third logical address in a second logical block of the memory; the physical page has a third physical address, and the processing unit updates a first mapping relationship to make it provide a mapping relationship between the first logical address and the third logical address and a mapping relationship between the second logical address and the third logical address, and stores the mapping relationship between the third logical address and the third physical address in the memory.


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