The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Feb. 12, 2016
Applicant:

Iii Holdings 2, Llc, Wilmington, DE (US);

Inventors:

Mark Bradley Davis, Austin, TX (US);

Barry Ross Evans, Austin, TX (US);

David James Borland, Austin, TX (US);

Assignee:

III HOLDINGS 2, LLC, Wilmington, DE (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); H04L 12/773 (2013.01); H04L 12/933 (2013.01); H04L 12/947 (2013.01); H04L 12/741 (2013.01); H04L 12/743 (2013.01); H04L 12/935 (2013.01); H04L 12/931 (2013.01); H04L 12/701 (2013.01); G06F 13/24 (2006.01); G06F 1/32 (2006.01); G06F 13/40 (2006.01); G06F 13/00 (2006.01); G06F 9/50 (2006.01); H04L 12/937 (2013.01); H04L 12/801 (2013.01);
U.S. Cl.
CPC ...
H04L 45/74 (2013.01); G06F 1/3234 (2013.01); G06F 3/0605 (2013.01); G06F 3/067 (2013.01); G06F 3/0631 (2013.01); G06F 9/5016 (2013.01); G06F 12/0284 (2013.01); G06F 13/00 (2013.01); G06F 13/24 (2013.01); G06F 13/40 (2013.01); H04L 45/00 (2013.01); H04L 45/60 (2013.01); H04L 45/7457 (2013.01); H04L 49/109 (2013.01); H04L 49/15 (2013.01); H04L 49/201 (2013.01); H04L 49/25 (2013.01); H04L 49/253 (2013.01); H04L 49/3009 (2013.01); H04L 49/351 (2013.01); H04L 49/356 (2013.01); H04L 47/10 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

A server apparatus comprises a plurality of server on a chip (SoC) nodes interconnected to each other through a node interconnect fabric. Each one of the SoC nodes has respective memory resources integral therewith. Each one of the SoC nodes has information computing resources accessible by one or more data processing systems. Each one of the SoC nodes configured with memory access functionality enabling allocation of at least a portion of said memory resources thereof to one or more other ones of the SoC nodes and enabling allocation of at least a portion of said memory resources of one or more other ones of the SoC nodes thereto based on a workload thereof.


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