The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Dec. 22, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Pei-Hsin Liu, Westford, MA (US);

Richard Lee Valley, Nashua, NH (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 1/32 (2007.01); H02M 1/08 (2006.01); H02M 1/42 (2007.01); G05F 1/575 (2006.01);
U.S. Cl.
CPC ...
H02M 3/1588 (2013.01); G05F 1/575 (2013.01); H02M 1/08 (2013.01); H02M 1/32 (2013.01); H02M 1/42 (2013.01); H02M 3/1584 (2013.01);
Abstract

A switch-mode power supply includes a transformer, a power transistor, pulse generation circuitry, and a dual ramp modulation (DRM) circuit. The power transistor is coupled to a primary coil of the transformer. The pulse generation circuitry is configured to generate a power transistor activation signal. The DRM circuit is coupled to the pulse generation circuitry. The DRM circuit is configured to generate a leading edge blank time signal that disables inactivation of the power transistor activation signal for a predetermined interval (a leading edge blank time) after a leading edge of the power transistor activation signal. The DRM circuit is also configured to generate a reset signal that inactivates the power transistor activation signal while the leading edge blank time signal is activated.


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