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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10134869 B1

PDFFull Text
Date of Patent:
Nov. 20, 2018

Filed:

Dec. 04, 2016

Method of manufacturing semiconductor device

Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Yasufumi Morimoto, Ibaraki, JP;

Kiyonobu Takahashi, Ibaraki, JP;

Morihiko Kume, Ibaraki, JP;

Assignee:

Renesas Electronics Corporation, Tokyo, JP;

Attorney:

Shapiro, Gabor and Rosenberger, PLLC

Primary Examiner:

Angel Roman

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/822 (2006.01); H01L 49/02 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/265 (2006.01); H01L 21/311 (2006.01); H01L 21/324 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/665 (2013.01); H01L 21/0206 (2013.01); H01L 21/265 (2013.01); H01L 21/28518 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/324 (2013.01); H01L 21/822 (2013.01); H01L 27/0629 (2013.01); H01L 28/20 (2013.01); H01L 29/6659 (2013.01); H01L 29/66553 (2013.01);
Abstract

To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.

Find Patent Forward Citations

Morimoto, Yasufumi. (2018). Method of manufacturing semiconductor device (U.S. Patent No. 10134869). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10134869

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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