The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Aug. 26, 2016
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Ho Kyun Ahn, Daejeon, KR;

Dong Min Kang, Daejeon, KR;

Yong-Hwan Kwon, Daejeon, KR;

Dong-Young Kim, Daejeon, KR;

Seong Il Kim, Daejeon, KR;

Hae Cheon Kim, Daejeon, KR;

Eun Soo Nam, Daejeon, KR;

Jae Won Do, Daejeon, KR;

Byoung-Gue Min, Sejong-si, KR;

Hyung Sup Yoon, Daejeon, KR;

Sang-Heung Lee, Daejeon, KR;

Jong Min Lee, Daejeon, KR;

Jong-Won Lim, Daejeon, KR;

Hyun Wook Jung, Daejeon, KR;

Kyu Jun Cho, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/404 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/401 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01);
Abstract

A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.


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