The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Oct. 31, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Inventors:

Xiaoguang Pei, Beijing, CN;

Chong Liu, Beijing, CN;

Zhilian Xiao, Beijing, CN;

Haisheng Zhao, Beijing, CN;

Zhilong Peng, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/77 (2017.01); H01L 27/02 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1244 (2013.01); H01L 21/77 (2013.01); H01L 27/02 (2013.01); H01L 27/12 (2013.01); H01L 27/127 (2013.01); H01L 27/1222 (2013.01); H01L 27/1262 (2013.01); H01L 29/66765 (2013.01); H01L 29/78669 (2013.01); H01L 27/1255 (2013.01);
Abstract

A method for manufacturing an array substrate, including: forming a plurality of first metal layer patterns on a base substrate which are independent from each other, each of the plurality of first metal layer patterns including an end at a non-display region of the array substrate; forming an insulating layer on the plurality of first metal layer patterns; and forming a semiconductor pattern on the insulating layer, a portion of semiconductor pattern is disposed directly opposite to the end of the first metal layer patterns.


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