The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Sep. 26, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Yusheng Xi, Beijing, CN;

Haichen Hu, Beijing, CN;

Ming Tian, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1339 (2006.01); H01L 29/786 (2006.01); G02F 1/1335 (2006.01); G02F 1/1368 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/1368 (2013.01); G02F 1/13394 (2013.01); G02F 1/133514 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01); G02F 2001/136295 (2013.01); H01L 29/7869 (2013.01);
Abstract

An array substrate, a method of producing the array substrate, and a display panel incorporating the array substrate are disclosed. The array substrate includes a substrate, a gate line, a data line, and a spacer. The gate line and the data line are arranged over the substrate. The spacer is arranged over the gate line and the data line. The gate line and/or the data line is provided with a via hole at a position corresponding to a spacer. In this manner, a problem of a display panel having gaps of different sizes after assembly because of non-uniform thicknesses of the gate line and/or the data line can be avoided, which, in turn, prevents inhomogeneous color in the display.


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