The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Apr. 27, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jung-woo Kim, Osan-si, KR;

Jae-min Jung, Seoul, KR;

Ji-yong Park, Hwaseong-si, KR;

Jeong-kyu Ha, Hwaseong-si, KR;

Woon-bae Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/48 (2010.01); H01L 23/498 (2006.01); H01L 23/29 (2006.01); H01L 23/00 (2006.01); H01L 23/488 (2006.01); H01L 33/62 (2010.01); H01L 23/492 (2006.01); H01L 25/16 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4985 (2013.01); H01L 23/29 (2013.01); H01L 24/32 (2013.01); H01L 23/488 (2013.01); H01L 23/4922 (2013.01); H01L 24/29 (2013.01); H01L 25/167 (2013.01); H01L 33/48 (2013.01); H01L 33/62 (2013.01); H01L 2924/143 (2013.01); H01L 2924/186 (2013.01);
Abstract

Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.


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