The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2018
Filed:
Dec. 18, 2013
Nvidia Corporation, Santa Clara, CA (US);
Jerome F. Duluk, Jr., Palo Alto, CA (US);
Cameron Buschardt, Round Rock, TX (US);
James Leroy Deming, Madison, AL (US);
Lucien Dunning, Santa Clara, CA (US);
Brian Fahs, Los Altos, CA (US);
Mark Hairgrove, San Jose, CA (US);
John Mashey, Portola Valley, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency.