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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10133550 B1

PDFFull Text
Date of Patent:
Nov. 20, 2018

Filed:

Dec. 29, 2015

Ternary digit logic circuit

Applicant:

Unist(ulsan National Institute of Science and Technology), Ulsan, KR;

Inventors:

Kyung Rok Kim, Ulsan, KR;

Sun Hae Shin, Ulsan, KR;

E San Jang, Ulsan, KR;

Jae Won Jeong, Ulsan, KR;

Assignee:

UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY), Ulsan, KR;

Attorney:

Klarquist Sparkman, LLP

Primary Examiner:

Alexander H Taningco

Assistant Examiner:

Kurtis R Bahr

Int. Cl.
CPC ...
H03K 3/29 (2006.01); G06F 7/48 (2006.01); H03K 19/0948 (2006.01); H03K 19/20 (2006.01); H03K 19/00 (2006.01); H03K 19/003 (2006.01); H03K 19/094 (2006.01); G06F 7/49 (2006.01);
U.S. Cl.
CPC ...
G06F 7/48 (2013.01); G06F 7/49 (2013.01); H03K 19/0016 (2013.01); H03K 19/00315 (2013.01); H03K 19/00361 (2013.01); H03K 19/0948 (2013.01); H03K 19/09429 (2013.01); H03K 19/20 (2013.01);
Abstract

A ternary logic circuit according to the present invention includes a pull-up device () and a pull-down device () connected in series between power voltage sources (Vand GND), and an input voltage (V) source and output voltage (V) source. When both the pull-up device () and the pull-down device () are turned off by an input voltage (V), both the pull-up device () and the pull-down device () operate as simple resistors which are affected only by an output voltage (V) and form a ternary digit ('1' state) through voltage division. When only one of the pull-up device () or the pull-down device () is turned on to allow a current to flow therethrough, V('2' state) or GND (“0” state) is output as the output voltage (V). Accordingly, a bit density can be remarkably increased.

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