The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Dec. 04, 2017
Applicant:

Kyocera Document Solutions Inc., Osaka, JP;

Inventor:

Thien-Phuc Nguyen Do, El Segundo, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 5/00 (2006.01); G06F 13/12 (2006.01); G06F 13/38 (2006.01); G06F 5/14 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 5/14 (2013.01); G06F 13/1673 (2013.01); G06F 13/4243 (2013.01); G06F 2205/126 (2013.01);
Abstract

Example systems and related methods may relate to a synchronous first-in-first-out (FIFO) data buffer. The synchronous FIFO data buffer may include a counter. The counter may (i) receive a plurality of signals and (ii) output a count of total entries in the FIFO. The FIFO may further include a status generator that may (i) receive the plurality of signals and the count of total entries, and (ii) outputs a status signal. The FIFO may further include a selection generator that may (i) receive the count of total entries, the write signal, and the read signal, and (ii) output a data enable signal and a multiplexor selection signal. The FIFO may further include a scalable N×M flip-flop memory structure. N may be a number of entries in the memory structure and M may be a number of bits using flip-flops.


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