The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Apr. 06, 2016
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Weimin Pan, Spring, TX (US);

Kangkang Shen, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 3/06 (2006.01); G06F 13/28 (2006.01); G06F 15/78 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0644 (2013.01); G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 9/50 (2013.01); G06F 13/28 (2013.01); G06F 15/7807 (2013.01);
Abstract

A system and method of partitioning host processing system resources is provided. An integrated circuit device having a plurality of processors or processing cores and a number of interfaces is portioned at boot into different hardware partitions based on the application needs of the host processing system. The technology provides a non-transitory memory storage including instructions; and a plurality of processors in communication with the memory. The integrated circuit device also includes a plurality of communication interfaces in communication with the processors. At least one of the plurality of processors executes instructions to configure a subset of the plurality of processors to a first hardware partition, and configure a different subset of the plurality of processors and at least one of the plurality of communication interfaces to a second hardware partition.


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