The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Feb. 28, 2017
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Michael Weiner, Nes Ziona, IL;

Hunglin Hsu, Cupertino, CA (US);

Nadav Klein, Tel Aviv, IL;

Junhua Xu, San Jose, CA (US);

Chia-Hung Chien, Sunnyvale, CA (US);

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 3/06 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/068 (2013.01); G06F 3/0659 (2013.01); G11C 11/4094 (2013.01);
Abstract

A Dynamic Random Access Memory (DRAM) controller includes a memory interface and a processor. The memory interface is configured to communicate with a DRAM including one or more memory banks. The processor is configured to receive Input/Output (I/O) commands, each I/O command addressing a respective memory bank and a respective row within the memory bank to be accessed in the DRAM, to further receive one or more indications, indicative of likelihoods that a subsequent I/O command will address a same row in a same memory bank as a previous I/O command, to adaptively set, based on the indications, a policy of deactivating rows of the DRAM, and to execute the I/O commands in the DRAM in accordance with the policy.


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