The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Sep. 02, 2015
Applicant:

Ultrasoc Technologies Ltd., Cambridge, GB;

Inventor:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/26 (2006.01); G06F 1/00 (2006.01); G06F 9/44 (2018.01); G01R 31/28 (2006.01); G01R 31/317 (2006.01); G06F 1/24 (2006.01); G06F 1/30 (2006.01); G06F 11/36 (2006.01); G06F 11/263 (2006.01); G06F 11/267 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31705 (2013.01); G01R 31/31721 (2013.01); G06F 1/24 (2013.01); G06F 1/26 (2013.01); G06F 1/30 (2013.01); G06F 1/32 (2013.01); G06F 1/3203 (2013.01); G06F 1/325 (2013.01); G06F 1/3206 (2013.01); G06F 1/3234 (2013.01); G06F 1/3246 (2013.01); G06F 1/3287 (2013.01); G06F 11/263 (2013.01); G06F 11/267 (2013.01); G06F 11/36 (2013.01); G06F 11/362 (2013.01); G06F 11/3636 (2013.01); G06F 11/3648 (2013.01); G06F 11/3656 (2013.01); G06F 15/7807 (2013.01);
Abstract

Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.


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