The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Nov. 14, 2014
Applicant:

Finisar Corporation, Sunnyvale, CA (US);

Inventors:

The'Linh Nguyen, San Jose, CA (US);

Daniel K. Case, Gilroy, CA (US);

Assignee:

FINISAR CORPORATION, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H04J 3/06 (2006.01); H04L 7/00 (2006.01); H04L 25/14 (2006.01); H04J 3/04 (2006.01); H03L 7/08 (2006.01); H03M 9/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); H03L 7/0807 (2013.01); H03M 9/00 (2013.01); H04J 3/047 (2013.01); H04J 3/0635 (2013.01); H04L 7/0041 (2013.01); H04L 25/14 (2013.01); H04L 7/033 (2013.01);
Abstract

A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.


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