IDiyas

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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10128829 B1

PDFFull Text
Date of Patent:
Nov. 13, 2018

Filed:

Feb. 22, 2016

Composite semiconductor device

Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Akio Nakajima, Sakai, JP;

Hisao Ichijoh, Kyotanabe, JP;

Assignee:

SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Jeffery S Zweizig

Int. Cl.
CPC ...
H03K 17/082 (2006.01); H01L 21/822 (2006.01); H01L 27/04 (2006.01); H03K 19/003 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H03K 17/10 (2006.01); H03K 17/567 (2006.01); H02M 7/00 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 17/082 (2013.01); H01L 21/822 (2013.01); H01L 23/3114 (2013.01); H01L 23/49503 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 24/40 (2013.01); H01L 27/04 (2013.01); H03K 17/0828 (2013.01); H03K 17/107 (2013.01); H03K 17/567 (2013.01); H03K 19/003 (2013.01); H01L 2224/40137 (2013.01); H01L 2224/40245 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13064 (2013.01); H02M 7/003 (2013.01); H03K 2017/6875 (2013.01);
Abstract

Provided is a composite semiconductor device that has a low on-resistance and a high load-short-circuit resistance. In a composite semiconductor device () including a normally-on first FET (Q) and a normally-off second FET (Q) that are cascode-connected to each other. In a case where a voltage applied to a drain of the first FET (Q) is 400 V, a relation of the following expression is satisfied: where a time elapsed after short circuit T represents a time elapsed after a time at which a load connected to the composite semiconductor device () starts to be short-circuited, RonQrepresents a value of an on-resistance of the second FET, VTHQrepresents a threshold voltage of the first FET, Idmaxrepresents a drain current of the first FET in a saturated state of the first FET when a gate voltage of the first FET is 0 V, and Idmax represents a drain current limited to an extent that breakdown of the first FET is prevented for the time elapsed after short circuit T of at least 2 μsec.

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