The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2018
Filed:
Jul. 03, 2017
Applicant:
Seoul Viosys Co., Ltd., Ansan-si, KR;
Inventor:
Shiro Sakai, Tokushima, JP;
Assignee:
Seoul Viosys Co., Ltd., Ansan-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/12 (2010.01); H01L 21/02 (2006.01); H01L 33/16 (2010.01);
U.S. Cl.
CPC ...
H01L 33/007 (2013.01); H01L 21/0242 (2013.01); H01L 21/0254 (2013.01); H01L 21/0265 (2013.01); H01L 21/02458 (2013.01); H01L 21/02639 (2013.01); H01L 21/02642 (2013.01); H01L 21/02664 (2013.01); H01L 33/0066 (2013.01); H01L 33/0075 (2013.01); H01L 33/0079 (2013.01); H01L 33/12 (2013.01); H01L 33/16 (2013.01);
Abstract
A method of manufacturing a semiconductor substrate including forming a first layer on a substrate, patterning the first layer to form a plurality of patterns spaced apart from one another, forming a second layer on the patterns to cover each of the patterns, heat-treating the second layer to form cavities in the patterns between the second layer and the substrate, and growing the second layer covering the cavities.