The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Nov. 29, 2016
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Armin Willmeroth, Friedberg, DE;

Ahmed Mahmoud, Munich, DE;

Enrique Vecino Vazquez, Munich, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/36 (2006.01); H01L 29/423 (2006.01); H01L 23/485 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 23/485 (2013.01); H01L 29/0619 (2013.01); H01L 29/36 (2013.01); H01L 29/4236 (2013.01); H01L 29/7813 (2013.01); H01L 29/0634 (2013.01); H01L 29/0696 (2013.01); H01L 29/0878 (2013.01); H01L 29/41766 (2013.01); H01L 2224/0603 (2013.01);
Abstract

Disclosed is a transistor device. The transistor device includes: a semiconductor body with an active region and a pad region; at least one transistor cell including a gate electrode dielectrically insulated from a body region by a gate dielectric, wherein the body region is arranged in the active region; an electrode layer arranged above the pad region and dielectrically insulated from the pad region by a further dielectric; and a gate pad arranged above the electrode layer and electrically connected to the electrode layer and the gate electrode of the at least one transistor cell. A thickness of the further dielectric is equal to or less than a thickness of the gate dielectric.


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